This invention relates to memory circuitry, and more specifically, to a memories which merge the bit lines of heterogeneous memory cells and concatenate rows of memory within single arrays, with a resultant sharing of bitlines, column decoders, and sense amplifiers.
The invention allows a single output bus for multiple memory components in lieu of one routed among the components. Traditionally, heterogeneous memory units have individual blocks of circuitry connected to shared data and address busses. For microcode data storage generally the address and data busses can have a width, for example, of 32, 64 or 128 bits, thus requiring a significant amount of routing area on integrated circuitry to connect memory blocks.
In addition, added area is needed, and power consumed, by replicating the functions of address decoders, array bitlines and sense amplifiers to detect data on bitlines for each heterogeneous memory. This loosely integrated approach, besides being larger and less power efficient, is more difficult to manage in the design hierarchy since the macrocells and all their subcells must be designed, debugged and maintained, instead of having a single merged macrocell.
The task of reducing power dissipation and circuit area required by architectures with mixed memories, by sharing bitlines, decoders, and sense amplifiers, and merging different memory cells into a single concatenated array, is alleviated, to some extent, by the systems described in the following U.S. patents, the disclosures of which are incorporated herein by reference: U.S. Pat. No. 5,325,323 to Nizaka; U.S. Pat. Nos. 5,323,342 & 5,313,418 to Wada et al; U.S. Pat. No. 5,313,420 to Masuoka; and U.S. Pat. No. 5,202,848 issued to Nakagawara.
The patent to Nakagawara discloses bitlines and column lines arranged alternately in common in each cell column, so as to be used in common by adjacent memory cells in a word line direction. The remaining patents are of similar interest.